The IBM eServer z990 microprocessor

Authors:
T. J. Siegel;E. Pfeffer;J. A. Magee
Affiliations:
IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, IBM Deutshland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany;IBM Sytems and Technology Group, 2455 South Road, Poughkeepsie, New York
Venue:
IBM Journal of Research and Development
Year:
2004

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Abstract

The IBM eServerTM z990 microprocessor implements many features designed to give excellent performance on both newer and traditional mainframe applications. These features include a new superscalar instruction execution pipeline, high-bandwidth caches, a huge secondary translation-lookaside buffer (TLB), and an onboard cryptographic coprocessor. The microprocessor maintains zSeries® leadership in RAS (reliability, availability, serviceability) capabilities that include state-of-the-art error detection and recovery.