The design of the fixed point unit for the z990 microprocessor

  • Authors:

  • Fadi Busaba;Timothy Slegel;Steven Carlough;Christopher Krygowski;John G. Rell

  • Affiliations:

  • IBM, Poughkeepsie, NY;IBM, Poughkeepsie, NY;IBM, Poughkeepsie, NY;IBM, Poughkeepsie, NY;IBM, Poughkeepsie, NY

  • Venue:
  • Proceedings of the 14th ACM Great Lakes symposium on VLSI
  • Year:
  • 2004

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Abstract

The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.