Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional verification of the CMOS S/390 parallel enterprise server G4 system
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
SimAPI—a common programming interface for simulation
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A methodology for the verification of a “system on chip”
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Automatic Vector Generation Using Constraints and Biasing
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
Automaton: An Autonomous Coverage-Based Multiprocessor System Verification Environment
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Automatic Functional Vector Generation Using the Interacting FSM Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A BNF-based automatic test program generator for compatible microprocessor verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The design of the fixed point unit for the z990 microprocessor
Proceedings of the 14th ACM Great Lakes symposium on VLSI
MicroGP—An Evolutionary Assembly Program Generator
Genetic Programming and Evolvable Machines
Automatic functional test program generation for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Decimal floating-point in z9: an implementation and testing perspective
IBM Journal of Research and Development
Stimulus generation for constrained random simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
z/CECSIM: an efficient and comprehensive microcode simulator for the IBM eServer z900
IBM Journal of Research and Development
Reconfigurable custom floating-point instructions (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Exploiting auto-adaptive µGP for highly effective test programs generation
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Functional verification of the IBM system z10 processor chipset
IBM Journal of Research and Development
Injecting floating-point testing knowledge into test generators
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
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This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP's) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors.