Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification of large ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A study in coverage-driven test generation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An Automatic Controller Extractor for HDL Descriptions at the RTL
IEEE Design & Test
Practical code coverage for Verilog
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
3.1: Practical FSM Analysis for Verilog
IVC-VIUF '98 Proceedings of the International Verilog HDL Conference and VHDL International Users Forum
Symbolic FSM traversals based on the transition relation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Abstraction: While the coverage-driven design validation is getting popular, it would be more convenient for users to have an automatic generator that can generate the input patterns to satisfy the coverage requirements. The symbolic techniques can be used to generate the desired input patterns easily for a specific state transition in a FSM. However, it is not practical for real designs because the memory requirement is often unmanageable. In this paper, we propose an automatic pattern generation engine that can overcome the memory issues for large circuits. It can generate all possible input combinations or notify that such cases will never happen for any specific state transitions. Because we can reasonably partition the HDL designs into the interacting FSM model, the peak memory requirement can be significantly reduced by using the "divide and conquer" strategy for those small FSMs. The experimental results show that we can indeed generate the required input patterns with reasonable memory requirement for the designs with thousands of registers.