Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Microprocessor design verification
Journal of Automated Reasoning
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A scalable formal verification methodology for pipelined microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Formal Verification of a Pipelined Microprocessor
IEEE Software
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Methodology for Processor Implementation Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An efficient design-for-verification technique for HDLs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A data flow fault coverage metric for validation of behavioral HDL descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Exploiting Retiming in a Guided Simulation Based Validation Methodology
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Design-for-Verification Technique for Functional Pattern Reduction
IEEE Design & Test
A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Automatic Functional Vector Generation Using the Interacting FSM Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transition-based coverage estimation for symbolic model checking
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Algorithms for compacting error traces
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
An automatic coverage analysis for systemc using UML and aspect-oriented technology
CSCWD'04 Proceedings of the 8th international conference on Computer Supported Cooperative Work in Design I
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The biggest obstacle in the formal verification of large designs istheir very large state spaces, which cannot be handled even bytechniques such as implicit state space traversal. The only viablesolution in most cases is validation by functional simulation. Unfortunately, this has the drawbacksof high computationalrequirementsdue to the large number of test vectors needed, and the lack of adequate coverage measures to characterize the quality of a given testset. To overcome these limitations, there has been recent interest inhybrid techniques which combine the strengths of formal verification and simulation. Formal verification-based techniques are usedon a test model (usually much smaller than the design) to derive a setof functional test vectors, which are then used for design validationthrough simulation. The test set generated typically satisfies somecoverage measure on the test model. Recent research has proposedthe use of state or transition coverage. However, no effort has beenmade to relate these measures to the coverage of design errors. Furthermore, the derivation of the test model remains largely ad-hoc,with few formal guidelines.We demonstrate that under a given set of assumptions, transitiontours on test models can be used for complete validation of an implementation against a specification, for a large and important classof designs that includes many programmable/hardwired, general-purpose processors/DSPs. A by-product of this study is specificguidelines for deriving the test model, motivated by the requirement of providing complete coverage of all errors. We illustrate theapplication of our methodology on a pipelined implementation of the DLX processor.