A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
On computing the minimum feedback vertex set of a directed graph by contraction operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective Co-Verification of IEEE 802.11a MAC/PHY Combining Emulation and Simulation Technology
ANSS '05 Proceedings of the 38th annual Symposium on Simulation
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This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.