Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A comparative study of design for testability methods using high-level and gate-level descriptions
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A distance reduction approach to design for testability
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A test synthesis technique using redundant register transfers
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High-level variable selection for partial-scan implementation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Transforming control-flow intensive designs to facilitate power management
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Testability Enhancement for Control-Flow Intensive Behaviors
Journal of Electronic Testing: Theory and Applications
Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An efficient design-for-verification technique for HDLs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Test strategies for BIST at the algorithmic and register-transfer levels
Proceedings of the 38th annual Design Automation Conference
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Design-for-Verification Technique for Functional Pattern Reduction
IEEE Design & Test
A Controller Testability Analysis and Enhancement Technique
EDTC '97 Proceedings of the 1997 European conference on Design and Test
How to Avoid Random Walks in Hierarchical Test Path Identification
ETW '00 Proceedings of the IEEE European Test Workshop
15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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In this study, we present a controllability measure for high-level circuit descriptions and a high-level synthesis-for-testability technique. Unlike many recent studies in the area of high-level synthesis for testability that focus on improving the testability of data paths, the objective of our approach is to improve the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.