Constant propagation with conditional branches
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Accurate static branch prediction by value range propagation
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Testability-based partial scan analysis
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Array SSA form and its use in parallelization
POPL '98 Proceedings of the 25th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements
Proceedings of the IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Partial Scan Selection Based on Dynamic Reachability and Observability Information
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
High-level testability analysis and enhancement for digital systems
High-level testability analysis and enhancement for digital systems
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
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This research applies formal data ow analysis and techniques to high-level DFT. Our proposed approach improvestestability of the behavioral-level circuit description (suchas in VHDL) based on propagation of the value ranges ofvariables through the circuit's Control-Data Flow Graph(CDFG). The resulting testable circuit is accomplished viacontrollability and observability computations from thesevalue ranges and insertion of appropriate testability enhancements, while keeping the design area-performanceoverhead to a minimum.