A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Design and synthesis for testability using architectural descriptions
Design and synthesis for testability using architectural descriptions
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Introduction to the Theory of Computation
Introduction to the Theory of Computation
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Partial Scan at the Register-Transfer Level
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for testing core-based systems-on-a-chip
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Test strategies for BIST at the algorithmic and register-transfer levels
Proceedings of the 38th annual Design Automation Conference
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Reducing Test Application Time in High-Level Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fast Test Generation for Circuits with RTL and Gate-Level Views
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low test application time resource binding for behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we present TAO, a novel methodology for high-leveltestability analysis and optimization of register-transfer levelcontroller/data path circuits. Unlike existing high-level testingtechniques that cater restrictively to certain classes of circuitsor design styles, TAO exploits the algebra of regular expressionsto provide a unified framework for handling a widevariety of circuits including application-specific integrated circuits,application-specific programmable processors, application-specificinstruction processors, digital signal processors and microprocessors.We also augment TAO with a design-for-test frameworkthat can provide a low-cost testability solution by examiningthe trade-offs in choosing from a diverse array of testability modificationslike partial scan or test multiplexer insertion in differentparts of the circuit. Test generation is symbolic and, hence,independent of bit-width. Experimental results on benchmark circuitsshow that TAO is very efficient, in addition to being comprehensive.The fault coverage obtained is above 99% in all cases.The average area and delay overheads for incorporating testabilityinto the benchmarks are only 3.3% and 1.1%, respectively. Thetest application time is comparable to that associated with gate-levelsequential test generators.