Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3-4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead du! e to this technique.