A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Fast hierarchical multi-level fault simulation of sequential circuits with switch-level accuracy
DAC '93 Proceedings of the 30th international Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incorporating testability considerations in high-level synthesis
Journal of Electronic Testing: Theory and Applications
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
Software accelerated functional fault simulation for data-path architectures
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Enhancing high-level control-flow for improved testability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
A test synthesis technique using redundant register transfers
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
High-Level VLSI Synthesis
Behavioral-Level Fault Simulation
IEEE Design & Test
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Partial Scan at the Register-Transfer Level
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
B-algorithm: A Behavioral-Test Generation Algorithm
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Analyzing Testability from Behavioral to RT Level
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Tutorial 3: Design and Test of Core-Based Systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partial Scan Testing on the Register-Transfer Level
Journal of Electronic Testing: Theory and Applications
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Improving testability during the earlystages of the design flow can have several benefits, includingsignificantly improved fault coverage, reduced test hardwareoverheads, and reduced design iteration times. This paper presents anoverview of high-level design methodologies that consider testabilityduring the early (behavior and architecture) stages of the designflow, and their testability benefits. The topics reviewed includebehavioral and RTL test synthesis approaches that generate easilytestable implementations targeting ATPG (full and partial scan) andBIST methodologies, and techniques to use high-level information forATPG.