Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An experimental analysis of the effectiveness of the circular self-test path technique
EURO-DAC '94 Proceedings of the conference on European design automation
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Evolving effective CA/CSTP: BIST architectures for sequential circuits
Proceedings of the 2001 ACM symposium on Applied computing
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Circular Self-Test Path for FSMs
IEEE Design & Test
CA-CSTP: A New BIST Architecture for Sequential Circuits
ETW '00 Proceedings of the IEEE European Test Workshop
Random pattern testability of memory control logic
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
Making the circular self-test path technique effective for real circuits
ITC'94 Proceedings of the 1994 international conference on Test
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