Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
An automated BIST approach for general sequential logic synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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The paper assesses the effectiveness of the Circular Self-Test Path BIST technique from an experimental point of view and proposes an algorithm to overcome the low fault coverage that often arises when real circuits are examined. Several fault simulation experiments have been performed on the ISCAS89 benchmark set, as well as on a set of industrial circuits: in contrast to the theoretical analysis proposed in [PKKa92], a very high Fault Coverage is attained with a limited number of clock cycles, but this happens only when the circuit does not enter a loop. This danger can nat be avoided even if clever strategies for Flip-Flops ordering, aimed at reducing the functional adjacency, are adopted. Instead, we suggest that loops can be avoided and fault coverage increased by carefully choosing the initial state, and we present an approach based on Binary Decision Diagrams and Symbolic Techniques to solve the problem.