Circular self-test path: a low-cost BIST technique
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Automatic incorporation of on-chip testability circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Multimode scan: Test per clock BIST for IP cores
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generation of embedded RAMs with built-in test using object-oriented programming
EURO-DAC '90 Proceedings of the conference on European design automation
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Making the circular self-test path technique effective for real circuits
ITC'94 Proceedings of the 1994 international conference on Test
Circular BIST with partial scan
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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An automated Built-In Self-Test (BIST) technique for general sequential logic is described. This BIST approach has been incorporated in a behavioral model synthesis system providing automated implementation of BIST in Very Large Scale Integration (VLSI) devices as well as Programmable Logic used at all levels of testing from device testing through system diagnostics. The BIST approach is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96 percent and the logic overhead incurred was between 9.7 and 18.9 percent.