Do you practice safe test? what we found out about your habits

Authors:
Cecil A. Dean;Yervant Zorian
Affiliations:
AT&T Bell Laboratories, Merrimack Valley, MA;AT&T Bell Laboratories, Princeton, NJ
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

Citing 8
Cited 0

Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques
A Partial Scan Method for Sequential Circuits with Feedback

IEEE Transactions on Computers
An automated BIST approach for general sequential logic synthesis

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The Test Access Port and Boundary-Scan Architecture

The Test Access Port and Boundary-Scan Architecture
ScanBist: A Multifrequency Scan-Based BIST Method

IEEE Design & Test
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Design for Testability A Survey

IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we look at the results of a year-long benchmarking effort in the area of IC-level design_for_testability (DFT). While visiting 10 leading edge companies, we looked at things such as their testability policies, reviews, process for adding testability, their intervals, fault coverage results, and if and where in the system the IC-level self-test was used.