Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Programmable BIST Space Compactors
IEEE Transactions on Computers
An Effective Multi-Chip BIST Scheme
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
A hybrid algorithm for test point selection for scan-based BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
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