Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Built-In Self-Testing Approach for Minimizing Hardware Overhead
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
Synthesis-for-testability of controller-datapath pairs that use gated clocks
Proceedings of the 37th Annual Design Automation Conference
Test strategies for BIST at the algorithmic and register-transfer levels
Proceedings of the 38th annual Design Automation Conference
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A wiring-aware approach to minimizing built-in self-test overhead
Journal of Computer Science and Technology
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This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5%).