High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
A test synthesis technique using redundant register transfers
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
A Behavior Model for Next Generation Test Systems
Journal of Electronic Testing: Theory and Applications
Synthesis of controllers for full testability of integrated datapath-controller pairs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
BISTing Datapaths under Heterogeneous Test Schemes
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Detecting undetectable controller faults using power analysis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Testing DSP cores based on self-test programs
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Inserting Scan at the Behavioral Level
IEEE Design & Test
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Structural BIST Insertion Using Behavioral Test Analysis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
1.3 Parallelism in Structural Fault Testing of Embedded Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
Journal of Electronic Testing: Theory and Applications
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
Keynote speech: testing methodologies for embedded systems and systems-on-chip
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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