Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
False path exclusion in delay analysis of RTL-based datapath-controller designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A scheme for integrated controller-datapath fault testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code Generation for Embedded Processors
Code Generation for Embedded Processors
A Built-In Self-Testing Approach for Minimizing Hardware Overhead
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-Level Test Generation Using Symbolic Scheduling
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A New FPGA for DSP Applications Integrating BIST Capabilities
Journal of Electronic Testing: Theory and Applications
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In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads.They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads.Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs) and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (99$%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0% and 1.5%, respectively. The test application time to achieve thehigh fault coverage for the whole controller-datapath