Algorithms for fast, memory efficient switch-level fault simulation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Sequential circuit fault simulation by fault information tracing algorithm: FIT
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On efficient concurrent fault simulation for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
On Fault Simulation for Synchronous Sequential Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New methods for parallel pattern fast fault simulation for synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
TAO: regular expression-based register-transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
Ten: A Concurrent Test Engineering Environment
IEEE Design & Test
Testability Implications of Performance-Driven Logic Synthesis
IEEE Design & Test
DFT guidance through RTL test justification and propagation analysis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Fast Test Generation for Circuits with RTL and Gate-Level Views
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Peak Power Reduction in Low Power BIST
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Reduced scan shift: a new testing method for sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
Dynamic fault dictionaries and two-stage fault isolation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes PROOFS, a super fast fault simulator for synchronous sequential circuits. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks.