Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Concurrent analysis techniques for data path timing optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Synthesis of application specific instruction sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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In this paper, we present design for testability (DFT) and hierarchicaltest generation techniques for facilitating the testingof application-specific programmable processors (ASPPs) andapplication-specific instruction processors (ASIPs). The methodutilizes the register transfer level (RTL) circuit description of anASPP or ASIP and tries to generate a set of test microcode patternswhich can be written into the instruction read-only memory(ROM) of the processor. These lines of microcode dictate a newcontrol/data flow in the circuit and can be used to test moduleswhich are not easily testable. The new control/data flow is used tojustify precomputed test sets of a module from the system primaryinputs to the module inputs and propagate output responses fromthe module output to the system primary outputs. If the derived testmicrocode cannot test all untested modules in the circuit, then testmultiplexers are added to the data path to test these modules andthus testability of all modules is guaranteed. This scheme has theadvantages of low area and delay overheads (average of 3.1% and0.4% respectively), high fault coverage (99.6% for all cases) andat-speed testing. Test generation times are about three orders ofmagnitude smaller than an efficient gate-level sequential test generator.Only one external test pin is required for the DFT method.