The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Automatic test generation for large digital circuits
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Critical path tracing - an alternative to fault simulation
25 years of DAC Papers on Twenty-five years of electronic design automation
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation
IEEE Transactions on Computers
RIDDLE: A Foundation for Test Generation on a High-Level Design Description
IEEE Transactions on Computers
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
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EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
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ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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DAC '97 Proceedings of the 34th annual Design Automation Conference
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Overall consideration of scan design and test generation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On fault modeling for dynamic MOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
High level hierarchical fault simulation techniques
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Modeling and simulation of real defects using fuzzy logic
Proceedings of the 37th Annual Design Automation Conference
Algorithms for Automatic Test-Pattern Generation
IEEE Design & Test
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
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DAC '84 Proceedings of the 21st Design Automation Conference
EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
Experience in functional-level test generation and fault coverage in a silicon compiler
EURO-DAC '90 Proceedings of the conference on European design automation
A proposed hardware fault simulation engine
EURO-DAC '91 Proceedings of the conference on European design automation
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IBM Journal of Research and Development
Dynamic Test Compaction for Bridging Faults
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
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Proceedings of the 2009 ACM SIGMOD International Conference on Management of data
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ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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Multiple test generation algorithms and techniques described in this paper have been integrated into a unified system which has successfully produced tests for unpartitioned LSSD logic structures of up to 50,000 logic gates. The design concepts behind the creation of a unified system are presented, as are actual results obtained on large logic structures. System usability was significantly enhanced by the same concepts that facilitated the integration of multiple algorithms and techniques.