Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Minimal Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
FedEx - a fast bridging fault extractor
Proceedings of the IEEE International Test Conference 2001
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Proceedings of the IEEE International Test Conference 2001
An Efficient Compact Test Generator for IDDQ Testing
ATS '96 Proceedings of the 5th Asian Test Symposium
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Compact test generation for bridging faults under I/sub DDQ/ testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
On the Characterization of Hard-to-Detect Bridging Faults
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We describe a dynamic test compaction procedure for four-way bridging faults.Under this fault model, a pair of lines g_i , g_j is associated with four bridging faults corresponding to two possible combinations of opposite values on g_i and g_j , and two options for the line whose value is faulty in the presence of the fault (either g_i or g_j ). Compaction is achieved by simultaneously considering faults that have a line g_i with a value 驴_i in common, such that the value 驴_i and g_i is affected by the presence of the fault.Faults with a common line g_i and value 驴_i differ only in the second line g_j of each pair of bridged lines, and the second lines only need to be assigned the value \bar \alpha _iin order to detect all the faults.This strong relationship between the faults allows us to derive tests that detect large numbers of these faults, resulting in compact test sets.