DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
IEEE Design & Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Stuck-open and transition fault testing in CMOS complex gates
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the Complexity of Estimating the Size of a Test Set
IEEE Transactions on Computers
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
Journal of Electronic Testing: Theory and Applications
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IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Test set enhancement for quality transition faults using function-based methods
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Test environment for embedded cores-based system-on-chip (soc): development and methodologies
MIC'06 Proceedings of the 25th IASTED international conference on Modeling, indentification, and control
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
Broadside and skewed-load tests under primary input constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents two algorithms for generatingcompact test sets for combinational and full scan circuits under the transition and CMOS stuck-open faultmodels; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. The test sets generated by MinTest are 30% smaller than the previouslypublished two-pattern test set compaction results forthe ISCAS85 and full scan version of the ISCAS89benchmark circuits.