Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Analysis and minimization of test time in a combined BIST and external test approach
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Generating efficient tests for continuous scan
Proceedings of the 38th annual Design Automation Conference
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Static Test Compaction and Test Pattern Ordering for Scan Designs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Two dimensional reordering of functional test data for compression by ATE
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
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Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST