DAC '96 Proceedings of the 33rd annual Design Automation Conference
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Minimal Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On Applying Set Covering Models to Test Set Compaction
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Defect-Oriented Test Scheduling
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An optimal test compression procedure for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A static compaction procedure to reduce test set size forscan designs and a procedure to order test patterns in order tosteepen the fault coverage curve are presented. The computationaleffort for both procedures is linearly proportional tothe computational effort required for standard fault simulationwith fault dropping. Experimental results on largeindustrial circuits demonstrate both the efficiency and effectivenessof the proposed procedures.