Optimal Scheduling of Signature Analysis for VLSI Testing
IEEE Transactions on Computers
Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Economic modeling of board test strategies
Journal of Electronic Testing: Theory and Applications - Special issue on economics of electronic design, manufacture and test
Test Economics in the 21st Century
IEEE Design & Test
Proceedings of the 39th annual Design Automation Conference
An Empirical Study on the Effects of Test Type Ordering on
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Static Test Compaction and Test Pattern Ordering for Scan Designs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Computers
A Note on System-on-Chip Test Scheduling Formulation
Journal of Electronic Testing: Theory and Applications
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit
IEEE Transactions on Computers
A Measure of Quality for n-Detection Test Sets
IEEE Transactions on Computers
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A test pattern ordering algorithm for diagnosis with truncated fail data
Proceedings of the 43rd annual Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Adaptive test elimination for analog/RF circuits
Proceedings of the 46th Annual Design Automation Conference
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Test time can be reduced by ordering tests so as to fail defective units early in the test process. An ordering algorithm requires information on the ability of tests to detect defective units. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this sub-set is representative. We develop a simple polynomial-time heuristic which uses the information from the sample set to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. Optimal test ordering algorithms require execution time which is exponential in the number of tests applied. In our experiments, the heuristic results in a significant reduction in test time for manufactured digital and analog ICs.