Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
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Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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ICCD '03 Proceedings of the 21st International Conference on Computer Design
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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IEEE Design & Test
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VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
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Proceedings of the conference on Design, automation and test in Europe
Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction
ETS '08 Proceedings of the 2008 13th European Test Symposium
Advances in variation-aware modeling, verification, and testing of analog ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose an adaptive test strategy that tailors the test sequence with respect to the properties of each individual instance of a circuit. Reducing the test set by analyzing the dropout patterns during characterization and eliminating the unnecessary tests has always been the approach for high volume production in the analog domain. However, once determined, the test set remains typically fixed for all devices. We propose to exploit the statistical diversity of the manufactured devices and adaptively eliminate tests that are determined to be unnecessary based on information obtained on the circuit under test. We compare our results with other similar specification-based test reduction techniques for an LNA circuit and observe 90% test quality improvement for the same test time or 24% test time reduction for the same test quality.