Artificial Neural Networks: A Tutorial
Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering
Test Generation for Accurate Prediction of Analog Specifications
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Specification Test Compaction for Analog Circuits and MEMS
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Top-down induction of decision trees classifiers - a survey
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
On the complexity of training neural networks with continuous activation functions
IEEE Transactions on Neural Networks
Adaptive test elimination for analog/RF circuits
Proceedings of the 46th Annual Design Automation Conference
Hierarchical parametric test metrics estimation: a ΣΔ converter BIST case study
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
RF specification test compaction using learning machines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-data volume optimization for diagnosis
Proceedings of the 49th Annual Design Automation Conference
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Because of the significant cost of explicitly testing an integrated, heterogeneous device for all its specifications, there is a need for a test methodology that minimizes test cost while maintaining product quality and limiting yield loss. The authors are developing a decision-tree-based statistical-learning methodology to compact the complete specification-based test set of an integrated device by eliminating redundant tests. A test is deemed redundant if its output can be reliably predicted using other tests that are not eliminated. To ensure the required accuracy for commercial devices, the authors employ a number of modeling and data-massaging techniques to reduce prediction error. Test compaction results produced for a commercial MEMS accelerometer are promising in that they indicate it is possible to eliminate an expensive mechanical test.