Statistical failure analysis of system timing
IBM Journal of Research and Development
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Artificial Intelligence - Special issue on relevance
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Proceedings of the conference on Design, automation and test in Europe - Volume 2
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical Test Compaction Using Binary Decision Trees
IEEE Design & Test
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This paper describes the implementation of a novel path-based learning methodology that can be applied for two purposes: (1) In a pre-silicon simulation environment, path-based learning can be used to produce a fast and approximate simulator for statistical timing simulation. (2) In post-silicon phase, path-based learning can be used as a vehicle to derive critical paths based on the pass/fail behavior observed from the test chips. Our path-based learning methodology consists of four major components: a delay test pattern set, a logic simulator, a set of selected paths as the basis for learning, and a machine learner. We explain the key concepts in this methodology and present experimental results to demonstrate its feasibility and applications.