IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Proceedings of the 37th Annual Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
From blind certainty to informed uncertainty
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
FPGA device and architecture evaluation considering process variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with two-sided constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Estimating path delay distribution considering coupling noise
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A linear-time approach for static timing analysis covering all process corners
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Small-delay defect detection in the presence of process variations
Microelectronics Journal
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Meshworks: a comprehensive framework for optimized clock mesh network synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An accurate sparse-matrix based framework for statistical static timing analysis
Integration, the VLSI Journal
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This paper presents a means for estimating parametric timing yield and guiding robust design-for-quality in the presence of manufacturing and operating environment variations. Dual emphasis is on computational efficiency and providing meaningful robust-design guidance. Computational efficiency is achieved by basing the proposed methodology on a post-processing step applied to the report generated as a by-product of static timing analysis. Efficiency is also ensured by exploiting the fact that for small processing/environment variations, a linear model is adequate for capturing the resulting delay change. Meaningful design guidance is achieved by analyzing the timing-related influence of variations on a path-by-path basis, allowing designers perform a quality-oriented design pass focused on key paths. A coherent strategy is provided to handle both die-to-die and within-die variations. Examples from a PowerPC microprocessor illustrate the methodology and its capabilities.