Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
High Performance Double-Gate Device Technology Challenges and Opportunities
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Materials and device structures for sub-32 nm CMOS nodes
Microelectronic Engineering
An evolutionary platform for developing next-generation electronic circuits
Proceedings of the 9th annual conference companion on Genetic and evolutionary computation
Proceedings of the 44th annual Design Automation Conference
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit and physical design of the MDGRAPE-4 on-chip network links
Proceedings of the 2008 international workshop on System level interconnect prediction
Proceedings of the 2008 international workshop on System level interconnect prediction
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Credit-based dynamic reliability management using online wearout detection
Proceedings of the 5th conference on Computing frontiers
System power management support in the IBM POWER6 microprocessor
IBM Journal of Research and Development
Proceedings of the 45th annual Design Automation Conference
An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs
Proceedings of the conference on Design, automation and test in Europe
Techniques for Design and Implementation of Secure Reconfigurable PUFs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A taylor series methodology for analyzing the effects of process variation on circuit operation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Statistical analysis of circuit timing using majorization
Communications of the ACM - A Blind Person's Interaction with Technology
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
Hardware Trojan horse detection using gate-level characterization
Proceedings of the 46th Annual Design Automation Conference
Variation-aware low-power synthesis methodology for fixed-point FIR filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The BubbleWrap many-core: popping cores for sequential acceleration
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design
Towards evolving industry-feasible intrinsic variability tolerant CMOS designs
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Optimising variability tolerant standard cell libraries
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
In-situ characterization and extraction of SRAM variability
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Carbon nanotube circuits: living with imperfections and variations
Proceedings of the Conference on Design, Automation and Test in Europe
Optimal sizing of configurable devices to reduce variability in integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Measuring the performance and intrinsic variability of evolved circuits
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Random variability modeling and its impact on scaled CMOS circuits
Journal of Computational Electronics
A case for opportunistic embedded sensing in presence of hardware power variability
HotPower'10 Proceedings of the 2010 international conference on Power aware computing and systems
Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch
Microelectronics Journal
Advanced Monte Carlo techniques in the simulation of CMOS devices and circuits
NMA'10 Proceedings of the 7th international conference on Numerical methods and applications
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Fitting standard cell performance to generalized Lambda distributions
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Modeling and performance evaluation of UTB SGOI devices scalable to 22 nm technology node
WSEAS Transactions on Circuits and Systems
Autonomous multi-processor-SoC optimization with distributed learning classifier systems XCS
Proceedings of the 8th ACM international conference on Autonomic computing
Differential public physically unclonable functions: architecture and applications
Proceedings of the 48th Design Automation Conference
The evolution of standard cell libraries for future technology nodes
Genetic Programming and Evolvable Machines
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Computers and Electrical Engineering
Journal of Computational Electronics
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates
Proceedings of the great lakes symposium on VLSI
Proceedings of the great lakes symposium on VLSI
Process variation in near-threshold wide SIMD architectures
Proceedings of the 49th Annual Design Automation Conference
The potential of Fe-FET for robust design under variations: A compact modeling study
Microelectronics Journal
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the Conference on Design, Automation and Test in Europe
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
Proceedings of the 50th Annual Design Automation Conference
Reliability challenges for electric vehicles: from devices to architecture and systems software
Proceedings of the 50th Annual Design Automation Conference
Improving PUF security with regression-based distiller
Proceedings of the 50th Annual Design Automation Conference
NBTI mitigation by optimized NOP assignment and insertion
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Strong PUFs and their (physical) unpredictability: a case study with power PUFs
Proceedings of the Workshop on Embedded Systems Security
ARGO: aging-aware GPGPU register file allocation
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Improving platform energy: chip area trade-off in near-threshold computing environment
Proceedings of the International Conference on Computer-Aided Design
Domino logic designs for high-performance and leakage-tolerant applications
Integration, the VLSI Journal
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.