Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A novel buffer circuit for energy efficient signaling in dual-VDD systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-Aware On-Chip Networks
IEEE Micro
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On-chip bus thermal analysis and optimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Handling inverted temperature dependence in static timing analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Journal of VLSI Signal Processing Systems
Thermal Impacts on NoC Interconnects
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-insensitive synthesis using multi-vt libraries
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new technique that takes advantage of the differing temperature dependences in low-voltage interconnect links and higher voltage transceivers. The link and transceiver are dynamically retimed as the system temperature changes. This delay borrowing enables the link to maintain a frequency requirement despite temperature-induced frequency variations in excess of 200%, and enables the link to operate at lower voltages than possible with a non-temperature aware link. In addition to improved tolerance of environmental variations, the proposed approach achieves energy savings of up to 40% in a commercial 65 nm technology, including the energy overhead of the temperature-aware system. Further, the delay borrowing system is shown to decrease temperature-induced delay variations by 85%.