Proceedings of the 43rd annual Design Automation Conference
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
A soft error robust and power aware memory design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Journal of Electronic Testing: Theory and Applications
Yield improvement and power aware low cost memory chips
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
Energy reduction through crosstalk avoidance coding in networks on chip
Journal of Systems Architecture: the EUROMICRO Journal
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Analysis of forward error correction methods for nanoscale networks-on-chip
Proceedings of the 2nd international conference on Nano-Networks
Adaptive stochastic routing in fault-tolerant on-chip networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Exploiting parity computation latency for on-chip crosstalk reduction
IEEE Transactions on Circuits and Systems II: Express Briefs
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
CPPC: correctable parity protected cache
Proceedings of the 38th annual international symposium on Computer architecture
A systematic methodology to develop resilient cache coherence protocols
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Status data and communication aspects in dynamically clustered network-on-chip monitoring
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
A novel NoC-based design for fault-tolerance of last-level caches in CMPs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Improving a fault-tolerant routing algorithm using detailed traffic analysis
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Addressing network-on-chip router transient errors with inherent information redundancy
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Dual-layer adaptive error control for network-on-chip links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
NoC-based fault-tolerant cache design in chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
International Journal of Computer Applications in Technology
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On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence, transient delay and logic faults are likely to reduce the reliability of across-chip communication. Given the reduced power budgets for SoCs, in this paper, we develop solutions for combined energy minimization and communication reliability control. Redundant bus coding is proved to be an effective technique for trading off energy against reliability, so that the most efficient scheme can be selected to meet predefined reliability requirements in a low signal-to-noise ratio regime. We model on-chip interconnects as noisy channels and evaluate the impact of two error recovery schemes on energy efficiency: correction at the receiver stage versus retransmission of corrupted data. The analysis is performed in a realistic SoC setting, and holds both for shared communication resources and for peer-to-peer links in a network of interconnects. We provide SoC designers with guidelines for the selection of energy efficient error-control schemes for communication architectures.