A soft error robust and power aware memory design

Authors:
Costas Argyrides;Carlos A. Lisboa;Luigi Carro;Dhiraj K. Pradhan
Affiliations:
Bristol University, Bristol, United Kingdom;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Bristol University, Bristol, United Kingdom
Venue:
Proceedings of the 20th annual conference on Integrated circuits and systems design
Year:
2007

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Abstract

A new RAM design, which is soft error robust and power aware, is proposed. The basic advantage of the proposed architecture is that it does achieve a considerable power saving potential, combined with potential for performance and reliability enhancements, while imposing an acceptable area overhead. Analytical models of the proposed architecture are presented and discussed.