DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Low-power color TFT LCD display for hand-held embedded systems
Proceedings of the 2002 international symposium on Low power electronics and design
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime
Proceedings of the 2003 international symposium on Low power electronics and design
Low Power 260 k Color TFT LCD One-Chip Driver IC
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A soft error robust and power aware memory design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a novel low power Charge Recycling SRAM (CR-SRAM) for portable TFT-LCD applications. In portable TFT-LCD applications, low power considerations are becoming more important for longer battery lifetime. For reducing the power consumption in SRAMs, the source-line, connected to the source terminals of the driver MOSFET's, is controlled, so that it is zero in the active mode and has a positive bias voltage in the stand-by mode. However, the overhead power consumed during the control of source-line voltage is considerable due to the large capacitive load on the source-line. Applying charge recycling technique to the source-line allows reducing the power dissipation of the source-biased SRAM. Moreover, by exploiting the sequential access pattern of TFT-LCD memory, the proposed CR-SRAM can efficiently reduce the power dissipation of the control circuit for charge recycling. The proposed CR-SRAM is implemented in a 0.18µm technology and shows 68% and 14% power reduction compared to Conventional SRAM (CON-SRAM) and Source-Biased SRAM (SB-SRAM), respectively. We also evaluate the power consumptions under various clock frequencies of row driver and temperatures. Experimental results show that the percentage of power savings due to charge recycling increases with the higher frequency and achieved a maximum of 25% at 250MHz.