Designs and their codes
Analysis of a BICS-Only Concurrent Error Detection Method
IEEE Transactions on Computers
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Proceedings of the 15th symposium on Integrated circuits and systems design
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Software pioneers: contributions to software engineering
Software pioneers: contributions to software engineering
A multiple bit upset tolerant SRAM memory
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
A soft error robust and power aware memory design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
Proceedings of the 45th annual Design Automation Conference
Increasing memory yield in future technologies through innovative design
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
IBM Journal of Research and Development
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New Mix codes for multiple bit upsets mitigation in fault-secure memories
Microelectronics Journal
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This paper presents a method to protect memories against multiple bit upsets and to improve manufacturing yield. The proposed method, called a Matrix code, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and multiple bit-upsets. The method is evaluated using fault injection experiments. The results are compared to well-known techniques such as Reed-Muller and Hamming codes. The proposed technique performs better than the Hamming codes and achieves comparable performance with Reed-Muller codes with very favorable implementation gains such as 25% reduction in area and power consumption. It also achieves reliability increase by more than 50% in some cases. Further, the yield benefits provided by the proposed method, measured by the yield improvements per cost metric, is up to 300% better than the ones provided by Reed-Muller codes.