Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Probability to Achieve TSC Goal
IEEE Transactions on Computers
Fault-tolerant computer system design
Fault-tolerant computer system design
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
IEEE Design & Test
Transient Fault Tolerance in Digital Systems
IEEE Micro
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Realistic Coverages of Voltage and Current Tests
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose in this paper a BICS-only method for concurrent error detection (CED) where a built-in current sensor (BICS) will be solely responsible for detecting faults and errors. Due to the wide applicability of the BICS, this approach can be applied directly to combinational circuits, sequential circuits, and even some analog circuits. A dependability model was developed to study the effectiveness of the proposed BICS-only method. The unsafe probability of the BICS-only design is sensitive to both fault coverage and testability of the BICS. When used in a duplicated CED system for fault masking, the system reliability is sensitive to the fault coverage, but not to the testability of the BICS. Next, we show that a dramatic increase in unsafe probability is possible if the BICS cannot make detection at every system clock cycle. A higher testability for BICS will, contrary to our intuition, make the unsafe probability higher. For duplicated CED applications, the reliability will be even lower than that of a nonredundant system. Therefore, the design criteria for BICS in the BICS-only method, in the order of importance, are: operating speed, fault coverage, and testability.