Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's
IEEE Transactions on Computers
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
An Improved Analytical Yield Evaluation Method for Redundant RAM's
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Estimating Burn-In Fall-Out for Redundant Memory
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computers
Fault clustering in deep-submicron CMOS processes
Proceedings of the conference on Design, automation and test in Europe
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The yield enhancement of field-programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
On the repair of memory cells with spare rows and columns for yield improvement
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
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A model with mixed Poisson statistics has been developed for calculating the yield for memory chips with redundant lines and for partially good product. The mixing process requires two parameters which are readily obtained from product data. The product is described in the model by critical areas which depend on the circuit's sensitivity to defects, and they can be determined in a systematic way. The process is represented in the model by defect densities and gross yield losses. These are measured with defect monitors independently of product type. This paper shows how the yield for any product can be calculated given the critical areas, defect density, and mixing parameter. Future yields are forecast by using expected improvements in defect densities. Examples show good agreement between actual and calculated yields.