A Universal Arithmetic Building Element (ABE) and Design Methods for Arithmetic Processors
IEEE Transactions on Computers
A Unified Reliability Model for Fault-Tolerant Computers
IEEE Transactions on Computers
Circuit implementation of fusible redundant addresses on RAMs for productivity enhancement
IBM Journal of Research and Development
IBM Journal of Research and Development
LSI yield modeling and process monitoring
IBM Journal of Research and Development
Equivalence of memory to "Random Logic"
IBM Journal of Research and Development
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
New Architecture and Algorithms for Degradable VLSI/WSI Arrays
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
Reconfigurable architectures for mesh-arrays with PE and link faults
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Run-time Reconfiguration Algorithm for VLSI Arrays
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
Reconfigurable architectures for VLSI processing arrays
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
On the reconfiguration algorithm for fault-tolerant VLSI arrays
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Efficient reconfigurable techniques for VLSI arrays with 6-port switches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In order to take full advantage of VLSI, new design methods are necessary to improve the yield and testability. Designs which incorporate redundancy to improve the yields of high density memory chips are well known. The goal of this paper is to motivate the extension of this technique to other types of VLSI logic circuits. The benefits and the limitations of on-chip modularization and the use of spare elements are presented, and significant yield improvements are shown to be possible.