A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
IEEE Transactions on Computers
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
IEEE Transactions on Computers
Interconnect Analysis and Synthesis
Interconnect Analysis and Synthesis
Fault-Tolerant Meshes with Small Degree
IEEE Transactions on Computers
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
An improved reconfiguration algorithm for degradable VLSI/WSI arrays
Journal of Systems Architecture: the EUROMICRO Journal
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
IEEE Transactions on Computers
On the reconfiguration of degradable VLSI/WSI arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power distribution analysis of VLSI interconnects using model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Techniques to determine subarrays when processing elements of VLSI arrays become faulty have been investigated extensively. These tend to identify the largest subarray that is possible without concentrating on the power efficiency of the resulting subarray. In this paper, we propose new techniques, based on heuristic strategy and dynamic programming, to minimize the interconnect length in an attempt to reduce power dissipation without performance penalty. Our algorithms show that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing the size of the subarray. Our evaluations show that, for a VLSI array of size 256 \times 256, the number of long interconnects in the subarray can be reduced by up to 95 percent for clustered faults and up to 50 percent and 73 percent for a random fault with density of 10 percent and 0.1 percent, respectively, when compared with the most efficient implementation cited in the literature. The interconnect power saving for a VLSI array of size 512\times 512 is by up to 11 percent for a random fault. We have also shown that interconnect power savings of up to 14 percent are possible for the cases investigated. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques for power efficient realizations. In addition, the lower bound of the performance has been proposed to demonstrate that the proposed algorithms are nearly optimal for the cases considered in this paper.