A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors

Authors:
Yung-Yuan Chen;Shambhu J. Upadhyaya;Ching-Hwa Cheng
Affiliations:
-;-;-
Venue:
IEEE Transactions on Computers
Year:
1997

Citing 9
Cited 11

A Fault-Tolerant Modular Architecture for Binary Trees

IEEE Transactions on Computers - The MIT Press scientific computation series
On yield, fault distributions, and clustering of particles

IBM Journal of Research and Development
Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays

IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches

IEEE Transactions on Computers
Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors

Computer - Special issue on wafer-scale integration
Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach

IEEE Transactions on Computers
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits

IEEE Transactions on Computers
Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy

IEEE Transactions on Computers
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions

IEEE Transactions on Computers
New Architecture and Algorithms for Degradable VLSI/WSI Arrays

COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
RACE: A Software-Based Fault Tolerance Scheme for Systematically Transforming Ordinary Algorithms to Robust Algorithms

IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
A Run-time Reconfiguration Algorithm for VLSI Arrays

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Low-power MIMO signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An improved reconfiguration algorithm for degradable VLSI/WSI arrays

Journal of Systems Architecture: the EUROMICRO Journal
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches

IEEE Transactions on Computers
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

IEEE Transactions on Computers
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the reconfiguration algorithm for fault-tolerant VLSI arrays

ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Efficient reconfigurable techniques for VLSI arrays with 6-port switches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	14.99

Visualization

Abstract

This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.