Efficient reconfigurable techniques for VLSI arrays with 6-port switches

Authors:
Wu Jigang;Thambipillai Srikanthan;Heiko Schröder
Affiliations:
Nanyang Technological University, Singapore;Nanyang Technological University, Singapore;School of Computer Science and Information Technology, RMIT University, Melbourne, Australia
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

Citing 6
Cited 1

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A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors

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An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays

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Self-Reconfigurable Mesh Array System on FPGA

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Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs

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On the reconfiguration of degradable VLSI/WSI arrays

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Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

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Abstract

This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large scale integration/wafer scale integration (VLSI/WSI) array under the row and column routing constraints, which has been shown to be NP-complete. The proposed VLSI/WSI array consists of identical processing elements such as processors or memory cells embedded in a 6-port switch lattice in the form of a rectangular grid. It has been shown that the proposed VLSI structure with 6-port switches eliminates the need to incorporate internal bypass within processing elements and leads to notable increase in the harvest when compared with the one using 4-port switches. A new greedy rerouting algorithm and compensation approaches are also proposed to maximize harvest through reconfiguration. Experimental results show that the proposed VLSI array with 6-port switches consistently outperforms the most efficient alternative proposed in literature, toward maximizing the harvest in the presence of fault processing elements.