Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

Authors:
Wu Jigang;Thambipillai Srikanthan;Xiaodong Wang
Affiliations:
-;-;-
Venue:
IEEE Transactions on Computers
Year:
2007

Citing 18
Cited 2

Configuration of VLSI Arrays in the Presence of Defects

Journal of the ACM (JACM)
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays

IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits

Computer
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors

IEEE Transactions on Computers
Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions

IEEE Transactions on Computers
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays

IEEE Transactions on Computers
Hardware-efficient and highly reconfigurable 4- and 2- track fault- tolerant designs for mesh-connected arrays

Journal of Parallel and Distributed Computing
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance

DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement

DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement

ISPAN '00 Proceedings of the 2000 International Symposium on Parallel Architectures, Algorithms and Networks
An improved reconfiguration algorithm for degradable VLSI/WSI arrays

Journal of Systems Architecture: the EUROMICRO Journal
Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column Rerouting

DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A Genetic Approach for the Reconfiguration of Degradable Processor Arrays

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches

IEEE Transactions on Computers
Efficient Spare Allocation for Reconfigurable Arrays

IEEE Design & Test
Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs

IEEE Transactions on Computers
Efficient reconfigurable techniques for VLSI arrays with 6-port switches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the reconfiguration of degradable VLSI/WSI arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Preprocessing and partial rerouting techniques for accelerating reconfiguration of degradable VLSI arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal approach for the development of intelligent industrial control components

International Journal of Computer Applications in Technology

Quantified Score

Hi-index	14.98

Visualization

Abstract

This paper deals with the issue of developing efficient algorithms for reconfiguring two-dimensional VLSI arrays linked by 4-port switches in the presence of faulty processing elements (PEs). The proposed algorithm reroutes the arrays with faults in both row and column directions at the same time. Unlike previous work, the compensation technique to replace the faulty PE is not restricted to the adjacent rows of the excluded row. Instead, we consider the neighbor rows of any faulty PE for compensation purposes. The non-faulty PEs lying in the excluded rows are also effectively utilized to form the maximal target arrays, making the proposed algorithm more efficient both in terms of the percentages of harvest and degradation of VLSI arrays for random and clustered faults. Empirical study shows that the improvement in harvest increases with increasing fault size, and is more notable for maximal square target arrays than for maximal target arrays. Our investigations show that the improvement can be up to 8% and 23% for a 256 x 256 VLSI array with random faults of size 25%, for maximal target arrays and for maximal square target arrays respectively.