An improved reconfiguration algorithm for degradable VLSI/WSI arrays

Authors:
Wu Jigang;Thambipillai Srikanthan
Affiliations:
Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore;Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2003

Citing 8
Cited 6

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Abstract

This paper discusses the NP-complete problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints. A new strategy for row selection in the logical array is proposed and Low's algorithm is simplified. Experimental results show that our algorithm is approximately 50% faster than the most efficient algorithm, cited in the literature, without loss of performance.