Efficient techniques and hardware analysis for mesh-connected processors

Authors:
Wu Jigang;Thambipillai Srikanthan;Schröder Heiko
Affiliations:
Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore;School of Computer Science and Information Technology, RMIT, Melbourne, Australia
Venue:
ICA3PP'05 Proceedings of the 6th international conference on Algorithms and Architectures for Parallel Processing
Year:
2005

Citing 5
Cited 0

Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions

IEEE Transactions on Computers
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays

IEEE Transactions on Computers
Self-Reconfigurable Mesh Array System on FPGA

DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An improved reconfiguration algorithm for degradable VLSI/WSI arrays

Journal of Systems Architecture: the EUROMICRO Journal
On the reconfiguration of degradable VLSI/WSI arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes efficient techniques to reconfigure a multi-processor array, which embedded in a 6-port switch lattice in the form of a rectangular grid. It has been shown that the proposed architecture with 6-port switches eliminate gate delays and notably increase the harvest when compared with one using 4-port switches. A new rerouting algorithm combines the latest techniques to maximize harvest without increase in reconfiguration time. Experimental results show that the new reconfiguration algorithm consistently outperforms the most efficient algorithm proposed in literature.