Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement
IEEE Transactions on Computers
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
IEEE Transactions on Computers
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays
IEEE Transactions on Computers
The Connection Network Class for Fault Tolerant Meshes
IEEE Transactions on Computers
Generation of Minimal Vertex Covers for Row/Column Allocation in Self-Repairable Arrays
IEEE Transactions on Computers
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy
IEEE Transactions on Computers
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
IEEE Transactions on Computers
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays
IEEE Transactions on Computers
Spare processor allocation for fault tolerance in torus-based multicomputers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
New Architecture and Algorithms for Degradable VLSI/WSI Arrays
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
A Run-time Reconfiguration Algorithm for VLSI Arrays
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An improved reconfiguration algorithm for degradable VLSI/WSI arrays
Journal of Systems Architecture: the EUROMICRO Journal
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences—Informatics and Computer Science: An International Journal
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
An improved replacement algorithm in fault-tolerant meshes
Proceedings of the 2007 Summer Computer Simulation Conference
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences: an International Journal
On the reconfiguration algorithm for fault-tolerant VLSI arrays
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Self organization on a swarm computing fabric: a new way to look at fault tolerance
Proceedings of the 7th ACM international conference on Computing frontiers
An FPGA-based fault-tolerant 2D systolic array for matrix multiplications
Transactions on computational science XIII
Efficient techniques and hardware analysis for mesh-connected processors
ICA3PP'05 Proceedings of the 6th international conference on Algorithms and Architectures for Parallel Processing
Hi-index | 14.99 |
A mesh-connected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some fault-tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reconfigurable processor array using single-track switches like Kung et al.'s model in [1]. The reconfiguration process in our model is executed based on the concept of the 驴compensation path驴 like Kung et al.'s method, too. In our model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and nonspare PEs while retaining the connections among nonspare PEs in the same manner in Kung et al.'s model. The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.