Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
A robust multiplexer-based FPGA inspired by biological systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: dependable parallel computer systems
Swarm intelligence: from natural to artificial systems
Swarm intelligence: from natural to artificial systems
IEEE Transactions on Computers
Swarm intelligence
Permanent Fault Repair for FPGAs with Limited Redundant Area
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Evolutionary Strategies And Intrinsic Fault Tolerance
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 3 - Volume 03
Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures
Journal of Parallel and Distributed Computing - Special issue on parallel bioinspired algorithms
Design of defect tolerant tile-based QCA circuits
Proceedings of the 18th ACM Great Lakes symposium on VLSI
POEtic tissue: an integrated architecture for bio-inspired hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Cooperative VLSI tiled architectures: stigmergy in a swarm coprocessor
ANTS'06 Proceedings of the 5th international conference on Ant Colony Optimization and Swarm Intelligence
Self-organization in communication networks: principles and design paradigms
IEEE Communications Magazine
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Recent studies have demonstrated the possibility to exploit Swarm Intelligence (SI) as an inspiration for the design of scalable VLSI tiled architectures exhibiting multitasking, adaptability, absence of centralized low-level control and fault-tolerance. SI approach to fault-tolerance, in principle, can be regarded as a reconfiguration-free cell-exclusion mechanism. The key elements at the basis of a reconfiguration free solution are: loose structure of the system, homogeneity, cooperative behaviors and self organization. In this paper, these self organization aspects, introduced in a recently developed multi-agent VLSI tiled architecture for array processing, expressly developed resorting to the SI inspiration, are presented along with some theoretical and experimental results. The architecture presents two forms of cell-exclusion (bypass and block of faulty elements), implementing self-adaptive behaviors rather than reconfiguration to face faults preserving system functionality. The proposed approach, exploiting indirect communications to provide workload spreading into the computing fabric, is also successful in reducing the effects of the presence of faulty elements without spare resources and with limited performance degradation.