A Fault-Tolerant Mapping Scheme for a Configurable Multiprocessor System
IEEE Transactions on Computers
A Gracefully Degradable VLSI System for Linear Programming
IEEE Transactions on Computers
Network Resilience: A Measure of Network Fault Tolerance
IEEE Transactions on Computers
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy
IEEE Transactions on Computers
Emulation of Hypercube Architecture on Nearest-Neighbor Mesh-Connected Processing Elements
IEEE Transactions on Computers
Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays
IEEE Transactions on Computers
A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability
IEEE Transactions on Parallel and Distributed Systems
A General Method for Maximizing the Error-Detecting Ability of Distributed Algorithms
IEEE Transactions on Parallel and Distributed Systems
An Efficient Method for Approximating Submesh Reliability of Two-Dimensional Meshes
IEEE Transactions on Parallel and Distributed Systems
Network resilience of star graphs: a comparative analysis
CSC '91 Proceedings of the 19th annual conference on Computer Science
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
Implementing Degradable Processing Arrays
IEEE Micro
Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors
IEEE Transactions on Computers
On Dependability Evaluation of Mesh-Connected Processors
IEEE Transactions on Computers
Self organization on a swarm computing fabric: a new way to look at fault tolerance
Proceedings of the 7th ACM international conference on Computing frontiers
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A new approach to the design of gracefully degradable processor arrays is discussed. Fault tolerance and graceful degradation are achieved by simultaneously reconfiguring the processor array and the algorithm in execution. Two types of algorithm reconfigurability are considered, namely, row reconfigurability (RR) and row-column reconfigurability (RCR). correspondingly, two array reconfiguration schemes are discussed, i.e., successive row elimination (SRE) and alternate row-column elimination (ARCE). It is shown that the computations of any algorithm executable in a processor array can always be (re) organized so that the resultant algorithm has the RR and/or RCR properties. Upper bounds on the increase in execution time of an algorithm due to reorganization of computations for reconfigurability are derived. Detailed analysis of performance and reliability is done for both SRE and ARCE reconfiguration schemes. These reconfiguration techniques are applicable to any processor array and suitable for VLSI technology.