Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
The Comparison Approach to Multiprocessor Fault Diagnosis
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Fault covering problems in reconfigurable VLSI systems
Fault covering problems in reconfigurable VLSI systems
Programmable Multichip Modules
IEEE Micro
| Hi-index | 0.00 |
Single-package processing systems are demanded by today's performance-driven network technology and multimedia-enabled applications. The single-packaging of large systems can be realized with wafer scale integration (WSI) technology, however, reliability issues related to large systems continue to plague WSI. Fault tolerance by way of reconfiguration has not found widespread use in WSI due to the extra real estate required for reconfiguration hardware. Multichip modules (MCMs) with their various implementation options provide an ideal technology for fault-tolerant processor arrays. A commercially-feasible MCM-based fault tolerance scheme that incurs no increase to primary circuit area is presented. The scheme facilitates the continued operation of a defective array that would otherwise be discarded. With minimal additional hardware and scheduling overhead, a healthy subarray is extracted from the original array such that original array topology is preserved. Details of the reconfiguration algorithm, switch control, and switch implementation are presented.